응시자격 |
1) JEDEC 표준화
- Must have MS at a minimum related in Electrical/Computer/Semiconductor Engineering
- Minimum MS + 6years experience in Memory or SoC field.
- Fluency in speaking & writing English is must required.
- Prefer working experience/knowledge/skills on a subset of the followings
※ Experience in JEDEC committee activity.
※ Memory or SoC product planning/marketing based on design/test experience
※ Good relationship or communication experience with ICT companies in worldwide
※ Processors(ARM or similar kinds preferred) and DRAM/storage hierarchy
※ Interface with processor & DRAM/storage
※ NAND Flash or DRAM architecture or design
※ SoC or NAND Flash controller architecture or design
※ Architecture or design for DRAM controller/eMMC/UFS controller in SoC
※ Strong communication skills and willingness to collaborate with others.
2) RFIC 설계
(1) Must have an MS or Ph.D. in Electronic Engineering
(2) Minimum MS + 1 years or Ph.D.
- 5 years experience in an architecture and/or implementation role in silicon
component design
- Must possess working knowledge/skills on a subset of the followings
- System/spec architect
※ RFIC architecture/spec design, knowledge of analog/digital communication systems
and modulation, system design down to circuit block specification level and its
verification with system simulation
- Rx circuit design
※ LNA, down mixer, IF VGA & filter, DCOC DAC, low noise bias, etc.
- Tx circuit design
※ DA, up mixer, IF VGA & filter, DCOC DAC, low noise bias, etc.
- LO circuit design
※ LC VCO, TSPC logic, charge pump, counter, frequency divider, DSM, ,etc.
- Aux. circuit design
※ op-amps, band-gap reference, I-reference voltage regulator, loop-back, etc.
- Digital design
※ RF calibration algorithm and coding, Digital front end architecture and design.
- On chip interconnect fabrics and IO interface(RFFE, I2C, SPI..), Performance
analysis/tuning and prototyping(FPGA) Strong cadence custom IC design Flow
※ schematic, custom layout, post-simulation
- Strong tool skill
※ Cadence, ADE, Spectre, Virtuse, Calibre, Verilog & VerilogA coding, Matlab,
C++ Skills in RTL design and verification and physical design.
- Ability to comprehend the RF transceiver’s system level requirement and to translate
it into the circuit level specifications.
- A thorough understanding of the physical layout requirement and ability to perform the
critical layouts
- Extensive experience in RF performance analysis(test, analysis, solution)
- System application
※ Extensive experience in RFIC PCB design, test software, application. |
